Integrated circuit design, and, more particularly, a simplified method of designing integrated circuits based on sub-components of cells and facilitating the transformation of the design between different foundries.
Modern electronic circuits and systems are build on the foundation of discrete semiconductor devices and integrated circuits. An integrated circuit consists of both active and passive elements formed on a silicon substrate. Metal layers are proved to interconnect the electrically isolated active and passive elements, defining particular logic and circuit functions.
A Metal Oxide Semiconductor (xe2x80x9cMOSxe2x80x9d) integrated circuit is one of the most popular type of integrated circuits in digital applications, where only an on-off transistor response is required. A particularly useful unit cell for the integrated circuit is a Complementary MOS (xe2x80x9cCMOSxe2x80x9d), which uses both n-channel and p-channel MOS field effect transistors (xe2x80x9cFETxe2x80x9d) on adjacent regions of the chip. CMOS is one of the most widely used unit cells for various integrated circuits. One of the advantages of using CMOS is that the standard dc power dissipation can be reduced to very small levels.
A gate array is an array of basic transistor cells, such as CMOS transistors, aligned regularly on a semiconductor substrate to form a generic layer. A first metal layer is added over the generic layer to provide interconnections between particular transistors to define particular logic gates. Two or more metal layers connect the logic gates to provide the circuit functions required by a customer. The metal layers are separated by insulating layers. The metal layers above the generic layer, are referred to as xe2x80x9cpersonalizationxe2x80x9d layers.
Computer aided design (xe2x80x9cCADxe2x80x9d) systems are widely used in designing integrated circuits (xe2x80x9cICxe2x80x9d), such as gate arrays, standard-cell based designs and other types of ICs. With the CAD system, a designer can access a library of pre-designed logical functional blocks, (referred to as xe2x80x9ccellsxe2x80x9d) of particular logic functions, such as NAND, NOR or AND logic circuits, to more rapidly develop a high level design. The cells may be laid out and connected by metal personalization layers to create an IC accomplishing the desired functions. Each cell of the cell library is usually treated as a discrete block and the minimum unit of IC design.
FIG. 1 illustrates the major process steps in designing an integrated circuit. First, a functional specification is created at step 110 which identifies the primary functions of the IC. A well known hardware description language (xe2x80x9cHDLxe2x80x9d) of a CAD system is often used at step 115 to specify the primary functions. At step 120, the behavior of the primary functions of the IC are then verified using a simulator. At step 125, the detailed logic for the design is created using a CAD program that synthesizes the logic from the HDL description using a cell library 160. Any commercial compiler can be used in this step. In addition to using predefined cells, the designer may also use custom patterned blocks, which may be manually crafted by a mask designer. The IC design is then verified at the logic level at step 130, using the functions and the timing characteristics of each cell in the cell library, to determine whether the design is functionally correct. Any commercial logic simulation tool may be used in this step. After the logic simulation, the logic circuits are placed on a master array and the cell interconnections are physically routed at step 135. Electronic circuit design is converted into physical layout design in this step. This process is typically automated using a placement and routing tool such as GARDS(trademark), available from Silicon Valley Research, Inc., Austin, Tex., or Gate Ensemble(trademark) from Cadence Design Systems, Inc., San Jose, Calif. Another post-layout timing verification is typically performed after the lay out process has been completed at step 140. At step 145, the foundry or an external mask supplier then uses the generated pattern data to create wafer used in the manufacture of the ICs. Prototype ICs are fabricated and tested at step 150. The design is modified, if necessary, to meet the performance specifications at step 155.
The IC fabrication process at a given foundry may differ from that at other foundries. For example, a more advanced fabrication facility may fabricate an IC with interconnections having narrower line widths and smaller spaces between adjacent layers than a less advanced facility. Transistors fabricated with smaller geometries generally have faster switching speeds and lower power than transistors having wider line widths. Depending on the foundry""s fabrication technologies and techniques, and the materials used, different physical geometric configuration constraints apply. These constraints are commonly referred to as xe2x80x9cgeometric design rulesxe2x80x9d or more simply, xe2x80x9cdesign rules.xe2x80x9d Design rules include dimensional specifications for the layout of a design such as minimum spacing between transistors, minimum separation between conductors to prevent shorting, minimum metal width, contact size and spacing between the contacts and minimum transistor length and width. For the IC to be fabricated at a different foundry with different design rules, the IC must be redesigned. Since this transformation into different design rules is a non-uniform transformation, it is a time consuming process increasing fabrication costs. For example, to transform an IC design based on cells to a different foundry with different design rules, each of the cells in the cell library, which typically includes several hundred cells, needs to be individually redesigned in accordance with the new design rules. Despite this cost, redesign of the IC is often necessary since fabrication at multiple foundries may be required to meet demand. Use of multiple foundries also reduces the risk of a supply shortage due to manufacturing problems at a particular foundry. A foundry may close necessitating the transfer of production to another foundry, as well.
Attempts have been made to facilitate IC design transformation between foundries. For example, U.S. Pat. No. 5,754,826 describes a method for transforming a rudimentary or generic circuit into two or more equivalent circuits for fabrication at different foundries in accordance with the design rules of those foundries. According to the ""826 patent, an IC is designed from a generic cell library. To customize an IC design to a specific foundry, a software program converts the plurality of generic cells into a plurality of cells adapted for the design rules for that specific foundry. A large number of generic cells are required.
U.S. Pat. No. 5,563,801 discloses a method for compensating for the slight variations in performance of transistors fabricated in different foundries, by adjusting the gate widths of the transistors to compensate for the performance variations. This patent only addresses part of the difficulties associated with transformation of IC designs between foundries.
A cell for defining a logic function or logic circuit of an integrated circuit is a combination of several distinct functional and geometrical sub-components, many of which are applicable to many or all cells. In accordance with the present invention, the sub-components are separately designed in accordance with a set of design rules and stored in a library in the memory of a computer, for use in designing an IC through a CAD system. The sub-components are referred to as xe2x80x9cprimitive cellsxe2x80x9d. A designer may use these primitive cells to design most of the logic functions, such as the INV, NOR, NAND logic circuits used in the design of an IC. An IC may now be viewed as a combination of a relatively small number of primitive cells, as compared to the several hundred cells in a cell library, facilitating the design of the IC and the transformation of the IC design for fabrication at another foundry in accordance with a different set of design rules.
To transform the IC design in accordance with the present invention, a corresponding library of primitive cells is designed in accordance with the design rules of the other foundry and the original primitive cells are replaced by the corresponding set of primitive cells in the IC design. Preferably, the outer length and width of each corresponding primitive cell are the same, even if the internal configuration of the corresponding primitive cells (i.e., size and number of contacts within the cells) differ. To maintain the same length and width, the outer dimension of the primitive cells are designed to meet the largest dimensional requirements of the design rules of the foundries where the IC may be fabricated. In addition, corresponding primitive cells are identified by the same name in each of the primitive cell libraries. Transformation may be readily accomplished through software by referencing the primitive cells in the primitive cell library to logic circuit cells containing those primitive cells in the logic circuit cell library used in designing the IC, such that changes in the configuration of the primitive cells automatically change the configuration of the logic circuit cells in the IC. Each type of primitive cell in the IC may individually be located and replaced by a corresponding primitive cell meeting the design rules of the second foundry through the software, as well.